module smg(rst,clk_out1,rx_data,seg,dig,end_sig);
input clk_out1,rst;
input end_sig;
input [7:0] rx_data;
output [2:0] dig;
output [7:0] seg;
reg [2:0] dig;
reg [7:0] seg;
reg [7:0] seg1,seg2;
reg [7:0] data;
reg smg_en=1'b0;
parameter _0=8'h3f,_1=8'h06,_2=8'h5b,_3=8'h4f,_4=8'h66,_5=8'h6d,_6=8'h7d,_7=8'h07,_8=8'h7f,_9=8'h6f;
//位选
always @(posedge clk_out1)
begin
	if(!rst)
	dig<=3'd7;
	else
	if(dig==3'd6)
	dig<=3'd7;
	else 
	dig<=dig-3'd1;
end

always @(end_sig)
begin
	smg_en<=~smg_en;
end
///////////////
//段选
always@(dig)
begin
	if(smg_en) 
	begin
		data<=rx_data; 		//接收完成，数据赋值
		case (dig)
		3'd7:seg<=seg1;
		3'd6:seg<=seg2;
		endcase
	end
	
end

always @(data[3:0])
begin
case(data[3:0])
		0:seg1<=_0;  
		1:seg1<=_1;
		2:seg1<=_2;
		3:seg1<=_3;
		4:seg1<=_4;
		5:seg1<=_5;
		6:seg1<=_6;
		7:seg1<=_7;
		8:seg1<=_8;
		9:seg1<=_9;
	endcase
end

always @(data[7:4])
begin
case(data[7:4])
		0:seg2<=_0;  
		1:seg2<=_1;
		2:seg2<=_2;
		3:seg2<=_3;
		4:seg2<=_4;
		5:seg2<=_5;
		6:seg2<=_6;
		7:seg2<=_7;
		8:seg2<=_8;
		9:seg2<=_9;
	endcase
end


endmodule
